Professor Daniela Bortoletto: Publications

Electroweak diboson production in association with a high-mass dijet system in semileptonic final states from $pp$ collisions at $\sqrt{s} = 13$ TeV with the ATLAS detector

ArXiv 2503.17461 (2025)

Search for a new pseudoscalar decaying into a pair of bottom and antibottom quarks in top-associated production in $\sqrt{s}$=13 TeV proton-proton collisions with the ATLAS detector

ArXiv 2503.17254 (2025)

Searches for direct slepton production in the compressed-mass corridor in $\sqrt{s}=13$ TeV $pp$ collisions with the ATLAS detector

ArXiv 2503.17186 (2025)

Search for heavy neutral leptons in decays of W bosons using leptonic and semi-leptonic displaced vertices in $\sqrt{s} = 13$ TeV $pp$ collisions with the ATLAS detector

ArXiv 2503.16213 (2025)

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

Journal of Instrumentation IOP Publishing 20:03 (2025) P03024

Authors:

G Alimonti, A Andreazza, F Arteche, MB Barbero, P Barrillon, R Beccherle, G Bonomelli, GM Bilei, W Bialas, D Bortoletto, G Calderini, A Caratelli, A Cassese, J Christiansen, E Conti, F Crescioli, M Daas, L Damenti, S D'Auria, F De Canio, G De Robertis, N Demaria, J DeWitt, Y Dieter, JJ John

Abstract:

The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.

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